| 摘要 |
PURPOSE:To enhance the performance of uniqueness of a frame synchronizing pattern by bringing the level of 3 bits or above in M bits of a frame synchronizing pattern to 1 and applying the code rule violation CRV to a level 1 for 2 bits or above except the level 1 of the first bit in the case of the CMI coding. CONSTITUTION:The level 1 is given to 3 bits or above (in this example, 4 bits) among M bits (in this case, M=8) of the frame synchronizing pattern and the CRV is applied to the level 1 of 2 bits or above (in this example, 1 of 2 bits) except the level 1 of the 1st bit. The uniqueness of the synchronizing pattern is enhanced by applying plural kinds of the CRV to the frame synchronizing pattern. Moreover, a level 0 is placed to a bit before the bit applies with the CRV to suppress the number of same code consecution after the CMI coding to 3 bits at maximum. |
