| 摘要 |
PURPOSE:To obtain a larger capacitor capacity with smaller cell area by utilizing the side face of a groove around a memory cell as a capacitor electrode, and forming a diffused layer having the same conductivity type as that of a substrate and higher impurity concentration in the bottom of the groove as an element isolating region between memory cells. CONSTITUTION:A groove 7 is formed by etching by RIE on a P-type Si substrate 1, a P<+> type diffused layer 12 is formed in the bottom of the groove 7 by ion implanting, and the interior of the groove is thermally oxidized to form a capacitor oxide film 8. Then, after an oxide film 11 on the upper part of the groove is removed, and an N<+> type diffused layer 6 is formed on the sidewall of the upper part of the groove by ion implanting. Thereafter, polySi is buried along the sidewall in the groove, and a storage electrode 9 is so formed as to be connected to the layer 6. Subsequently, a thin oxide film is formed by thermally oxidizing as a capacitor oxide film 10. Further, the oxide film on the bottom of the groove is removed, polysilicon is deposited in the groove to form a cell plate 11, and is brought into contact with the layer 12 in the bottom of the groove 7. |
