发明名称 POLYPHASE OSCILLATOR
摘要 PURPOSE:To prevent the delay in phase and to attain high accuracy, by constituting a device with a counter, flip-flops and a phase locked loop without using a current transformer and a transformer. CONSTITUTION:A counter 20 counts a clock from a clock oscillator 10, a pulse is outputted from terminals 0, 1, 2,-i, -n in time series and this is repeated. A binary flip-flop 30 is inverted with a carry signal of the counter. That is, the binary flip-flop generates a rectangular wave frequency-dividing the clock by 2n. This is inputted to a D type flip-flop data terminal, and a phase delay amount of the output of the D type flip-flop depends that to which output terminals of the counter a trigger terminal of the D type flip-flop is connected. The output of the D type flip-flop is outputted via a phase locked loop.
申请公布号 JPS58107730(A) 申请公布日期 1983.06.27
申请号 JP19810207725 申请日期 1981.12.22
申请人 YOKOGAWA DENKI SEISAKUSHO KK 发明人 SHINDOU SHIYOUTAROU
分类号 H03L7/16;H03L7/22;(IPC1-7):03L7/16 主分类号 H03L7/16
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