| 摘要 |
PURPOSE:To reduce the converting time, by changing the clock frequency of a counter in response to the converting error, in controlling an up/down converter through the polarity of converting error. CONSTITUTION:An up/down counter 12 receives a converting error polarity signal from a comparator 10 via a photocoupler 11 and up/down-counts the clock of a clock oscillating circuit A. This count output is converted into an analog value at a digital pulse width conversion circuit 14, a photocoupler 16 and a pulse width-analog conversion circuit 17, and compared with an input signal at a comparat or 10. Both values are absolute value signal of conversion error at a bridge circuit via buffers 18, 19 and change the frequency of the oscillating circuit A via a photocoupler 25, allowing to reduce the conversion time. |
