| 摘要 |
PURPOSE: To improve the flexibility of programmable property by containing an analog function block, a programmable logic circuit and an inter-block connecting means that connects them. CONSTITUTION: This chip includes a programmable logic circuit 10 which is combined with a phase lock loop 20 as an analog function block, and the circuit 10 contains a programmable AND array 22 which generates an output of a product term, an output block 24 and an input circuit block 40. An output from an OR gate 50 forms a data output of the circuit 10, while an output of an OR gate 52 forms a load activation output of the circuit 10. And an output of an OR gate 54 forms a HOLD output of the circuit 10 and further, another product term forms a RESET output from the circuit 10. Thereby, the chip has flexibility and can also improve cost efficiency. |
