| 摘要 |
<p>A phase detecting circuit for detecting a phase differential between a reference clock and a bit timing extracted from a demodulated signal, which is derived from a modulation wave modulated by a digital signal. The circuit successfully eliminates points of discontinuity in the phase detection characteristic of a phase detector and, therefore, accurately determines a phase differential between the bit timing and the reference clock with no regard to the magnitude of the phase differential of an input. An absolute value averaging circuit is provided for averaging the absolute values of a pluality of consecutive outputs of a phase detector. A sign majority decision circuit is provided for producing one of positive and negative signs of the consecutive outputs of the phase detector which is decided by majority. Further, a multiplier is provided for multiplying an output of the absolute value averaging circuit and an output of the majority decision circuit, the resulting product being delivered as a phase differential.</p> |
