发明名称 PARTIAL PRODUCT FORMING CIRCUIT
摘要 PURPOSE:To reduce the number of partial products and to attain rapid operation in the case of applying the title circuit to a multiplier by forming a partial product of a multiplier consisting of 3 bits. CONSTITUTION:The partial product forming circuit has seven multipliers 3 to 9 respectively having multiplying factors of '0', '4', '8', '0', '1', '-2', '-1', two selecting circuits 11, 12, a control circuit 10 for generating control signals for the selecting circuit 11, 12, and adder 13. When the combination of a multiplier input terminal 2 for a multiplier consisting of 3 bits is (A2,A1,A0), relation among a multiplicand input 'X' to the combination of (A2,A1,A0), the outputs of the selecting circuits 11, 12 and a partial product output 'Y' is expressed so that the circuit 11 outputs '0' in case of (0,0) in the combination (A2,A1), 4X in case of (0,1) and (1,0) and 8X in case of (1,1) and the circuit 12 outputs '0' in case of (0,0) in the combination (A1,A0), X in case of (0,1), -2X in case of (1,0), and -X in case of (1,1). Thus, a partial product having a binary code in the combination of (A2,A1,A0) as a factor can be obtained from the output of the adder 13 by using said combination. Consequently rapid operation can be attained.
申请公布号 JPH0250723(A) 申请公布日期 1990.02.20
申请号 JP19880201223 申请日期 1988.08.12
申请人 NEC CORP 发明人 SHIRATORI AKIHIRO
分类号 G06F7/53;G06F7/483;G06F7/52;G06F7/523 主分类号 G06F7/53
代理机构 代理人
主权项
地址