发明名称 PACKET INFORMATION TRANSFER CONTROL SYSTEM
摘要 PURPOSE:To execute the composite exchange processing composed of line exchange and packet exchange by providing a time division switch to exchange information of 64kb/s, an interface circuit to execute the input processing to the time division switch and an interface circuit to execute the output processing. CONSTITUTION:In the case of connecting data terminal equipments 1, 2, paths (1), (2) of the time division switch 9 are connected. The path is fixedly connected by the time division switch 9 between a packet signal processing control section 152 and a packet switch control module 17 in the packet signal processing. The information subjected to packet processing is sent between the data terminal equipments 1, 2, processors 524, 1524, and packet switch control modules 10, 17. The transfer of packet information is controlled while the processor 1524 executes the packet multiplex processing to transfer the packet information to plural data terminal equipments.
申请公布号 JPH0250645(A) 申请公布日期 1990.02.20
申请号 JP19880201453 申请日期 1988.08.12
申请人 NEC CORP 发明人 KOBAYASHI TSUNEO
分类号 H04L12/02 主分类号 H04L12/02
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