| 摘要 |
PURPOSE:To reduce the number of elements and to realize a unit with an IC whose chip area is considerably reduced by using a read-only memory for execution of binary-coded decimal conversion. CONSTITUTION:An input data latch A6 latches contents of a data bus 20 at the timing of a clock signal CKA, and its output is data to be operated of a 4-bit full adder 1. The output of an input data latch B7 is data to be operated of the adder 1 also. An external carry signal CIN11 is inputted to the 4-bit adder 1, and subtraction is performed when an addition/subtraction switching signal A/S12 is in logical level '1', and addition is performed when it is in level '0', and five bits are outputted. A circuit 5 judges whether data to be operated is a numeral which can be expressed with binarized decimal or not. When the result is not '0' to '9', outputting whether an error or correct one is selected. |
