| 摘要 |
PURPOSE:To eliminate an offset region and to improve the device characteristics by a method wherein second electrodes and third electrodes are successively arranged in series with first electrodes, in between and the second electrodes and the third electrodes are provided as the gates of memory cell transistors and the first electrodes are provided as the gates of selector transistors. CONSTITUTION:First polycrystalline silicon electrodes 3 are provided as the gates of selector transistors TS and second polycrystalline silicon electrodes 5 and third polycrystalline silicon electrodes 7 operate as the gates of memory cell transistors T1-T6. In this constitution, the memory cell transistors T1, T2, T4 and T6 are transistors with implanted impurity for data programming and provided as depletion transistors. On the other hand, the selector transistors TS and the memory cell transistors T3 and T5 are provided as enhancement transistors. |
