| 摘要 |
PURPOSE:To improve latchup resistance characteristic by completely enclosing a MOS transistor of a peripheral circuit with an N-type latchup preventive layer connected to a fixed potential supply terminal. CONSTITUTION:A MOS transistor 101 for a memory cell is provided on a first element forming region made of P-type well 103' and P-type buried layer 107 provided selectively on an N-type epitaxial layer 105. A MOS transistor 101 for a peripheral circuit is provided on a second element forming region made of a P-type second well 103 on the layer 105. The layers 103, 105 are surrounded by an N-type latchup preventive layer 104 connected to a power source potential supply terminal, the side face of the layer 104 is of a P-type leading region 12, and connected to electrode wirings made of a polycrystalline silicon layer 116a, a W layer 116b, and an Al layer 116c. Thus, latchup resistance characteristics are improved. |
