| 摘要 |
<p>PURPOSE:To quickly obtain an output signal synchronizing with a clock pulse by using the D-FFs containing the master set terminal and the master reset terminals over two stages. CONSTITUTION:The asynchronous signals 11 are inputted to the input terminals D1 and D2 of the D-FF 1 and 2 containing the master set and reset terminals respectively. At the same time, the clock pulses 100 are inputted to the clock input terminals CP of the FF 1 and 2 respectively. The signal 11 is inputted to a master reset terminal MR1 of the FF 1 via a delay circuit 3. When the signal 11 changes to '1' from '0' before a period of set-up time, the terminal MR1 is negated before the rise of the pulse 100. Then the signal 11 is sampled and '1' is held by the FF 1 and 2 respectively. Thus the output 10 of the FF 1 and the output synchronizing signal 20 of the FF 2 are set at '1'. Then the signal 20 is set at '0' when the signal 11 is changed to '0' from '1'.</p> |
