| 摘要 |
A pipeline controlling system executing a preceding instruction in parallel with calculation of an effective address of a succeeding instruction, comprises a first instruction register for storing and holding the preceding instruction, which is in an execute phase; a second instruction register for storing and holding the succeeding instruction, which is in an effective address phase; a register file for storing and holding information to be used for executing the preceding instruction and for calculating the effective address of a succeeding instruction; an effective address calculating portion for calculating the effective address of the succeeding instruction; a comparator for comparing information for designating in the register file a storing location of information to be used for executing the preceding instruction with information for designating in the register file a storing location of information to be used for calculating the effective address of the succeeding instruction; and a controlling circuit for controlling the effective address calculating portion such that the calculation of the effective address of the succeeding instruction is carried out in parallel with the execution of the preceding instruction according to information in a pipeline controlling region and according to a result of the comparison of the comparator, when the comparator outputs a coincidence signal and the information in the pipeline controlling region indicates that the contents of the register file is not changed.
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