发明名称 WRITE INHIBITING SYSTEM AT THE TIME OF RUNAWAY OF CPU
摘要 PURPOSE:To prevent write from being executed to a signal control part to an external device and a semiconductor memory part until it is detected that a CPU has run away by constituting the title system so that a write inhibition control circuit nullifies other write than a prescribed procedure. CONSTITUTION:In the case of executing write to a semiconductor memory part 12 and a signal control part 13 to the outside, whether write by a prescribed procedure is being executed or not is monitored in a write inhibition control circuit 15, and when it is not being executed as prescribed, a write signal B is not generated. Also, the write inhibition control circuit 15 sets other part than a nonvolatile storage part 11 and a runaway monitoring timer part 14 so that it becomes a write inhibited state again when it is brought to access once, even if a CPU 10 executes an operation for writing prescribed data to a prescribed address. In such a way, when the CPU 1 has run away, it does not occur that write is executed to the semiconductor memory part 12 and the signal control part 13 to the outside before the CPU 10 is reset by the runaway monitoring timer part 14.
申请公布号 JPH0241539(A) 申请公布日期 1990.02.09
申请号 JP19880193275 申请日期 1988.08.02
申请人 FUJITSU LTD 发明人 IMABAYASHI TAKEHIRO
分类号 G06F12/16;G06F11/00;G06F12/14;G06F21/02 主分类号 G06F12/16
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