| 摘要 |
<p>PURPOSE:To improve the use efficiency of an in-chip device as compared with a case wherein timer circuits are provided individually by adding a transfer controller to the DMA unit and decreasing idle combinations of devices. CONSTITUTION:A CPU 11 outputs a D/T signal 12 to a timer/DMA controller 2, which operates as a DMA controller when the D/T signal 12 is at high level, but functions as a timer when at low level. For DMA service, the number of times of transfer is set in a counting register 3 and decreased in synchronism with the DMA transfer. When the controller 2 selects timer operation, the value obtained by dividing a time to be closed by the period of a clock is set in the register 3, whose contents are decreased in synchronism with the clock. This operation is repeated and when the value in the register 3 becomes minus, a borrow signal 6 is inputted to the controller 6 and the completion of determined-frequency DMA transfer is detected. Here, a terminal count signal 8 is outputted to indicate the transfer end to the outside.</p> |
