| 摘要 |
PURPOSE:To reduce the total shift and addition frequencies necessary for the multiplication of a single time to perform the multiplication at a high speed by dividing the multiplication every two bits to perform the shift and addition operations every two bits. CONSTITUTION:A multiplier (A) is divided every two bits and set at an accumulator 4, and a multiplicand (B) is set at an input latch 5b of an arithmetic logic unit ALU 5. At the same time, a partial product (C) is set at a latch 5a. A control signal output circuit 9 decides a mode (M1) where the C is outputted as it is, a mode (M2) where the B is added to the C, a mode (M3) where the double B is added to the C, or a mode (M4) where the B is subtracted from the C according to the values of the lower rank bits of the B. Then the circuit 9 produces a signal S. The ALU 5 carries out a process based on the signal S and sets the result of this process at the latch 5a or 5c. Such operations are repeated by n/2-bit times to complete a multiplication process (AXB) except a correction process. As a result, the total frequency of additions can be decreased and the multiplication is carried out at a high speed. |
