| 摘要 |
<p>PURPOSE:To detect the synchronized output signal of an asynchronous input signal by inputting the output of an asynchronous input circuit to two buffer circuits having different threshold levels and outputting the exclusive OR of the output signals of the buffer circuits. CONSTITUTION:The asynchronous input signal S1 inputted to an input terminal 1 of an IC is transmitted to 1st and 2nd FF 4a and 4b via an input buffer 2 consisting of two inverters 3a and 3b and synchronized with the clock signals phi1 and phi2. Then the output signal SQ5 of the FF 4b is transmitted to an internal circuit 13 of an IC via an inverter 1 from an output terminal theta5 of the FF 4b. The output terminal Q5 outputs an intermediate level M and at the same time the output signal S6 of the inverter also outputs a nonlogical intermediate level M. In such a case, an inverter IH having the threshold level H higher than the level M outputs 1(SH). While an inverter IL having the threshold level L lower than the level M outputs 0 respectively. Then a deciding signal S0 that defines the state as an exclusive OR is outputted to a register 10 from a deciding circuit 9.</p> |
