发明名称 ADDRESS QUALIFYING SYSTEM
摘要 PURPOSE:To increase the degree of freedom for assigning an area of an array variable when generating a program, by coupling and combining a value of a page register and a value of an address operand, enlarging the bit length, and after that, executing the addition of index qualification. CONSTITUTION:An adding circuit 8 has an operation capacity of (p) and (n) bit length when an output of a page register 2 and an output of a direct address register 4 are made (p) bits and (n) bits, respectively, and adds a data of (p)+(n) bits, which has coupled and combined the output of the page register 2 and the output of the direct address register 4, and an output data of a selector 5. When an external instruction is transferred, an instruction code and an address operand (a) being a direct instructing address are entered in an instruction register 1. In this case, a page is entered in the page register 2, and also in an index register 3, an index value is entered.
申请公布号 JPS58114246(A) 申请公布日期 1983.07.07
申请号 JP19810212780 申请日期 1981.12.28
申请人 FUJITSU KK 发明人 KARIBE HIROHISA;MATSUMURA TOSHIHIKO
分类号 G06F9/34;G06F9/355;G06F9/44 主分类号 G06F9/34
代理机构 代理人
主权项
地址