发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To assure higher withstand voltage without lowering a switching speed even with shallow diffusion into a gate by providing an N type high concentration buried layer only just under a p type anode layer. CONSTITUTION:A p type gate layer 15, and an N type cathode layer 16, a p type silicon substrate 11, and a p type high concentration separation layer 13, all jointly constituting a transverse PNPN thyristor are all set to low voltage sides of the same potential, and a p type anode layer 17 is set to a high voltage side. There is no N type high concentration buried layer just under the gate layer 15. This allows a depletion layer 18 to ascend from the p type substrate. Hereby, any bend of the depletion layer 18 at the end of the gate layer can be moderated and breakdown strength can be raised even with shallow diffusion into the gate layer. Further, since there is existent an N type high concentration buried layer 12 just under the anode layer 17, a switching speed of the device is not lowered.
申请公布号 JPH0239470(A) 申请公布日期 1990.02.08
申请号 JP19880189502 申请日期 1988.07.28
申请人 MATSUSHITA ELECTRON CORP 发明人 IMAHASHI MANABU
分类号 H01L21/74;H01L29/06;H01L29/08;H01L29/74 主分类号 H01L21/74
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