| 摘要 |
<p>Disclosed is a solid state disk emulator system for significantly improving access time, i.e., improving both the seek time and the rotational latency. The disk emulator complies with the SMD interface convention and thus to the central processor and the SMD disk controller (107), the disk emulator appears as a disk with virtually a zero access time. In one embodiment, the primary systems of the disk emulator are a 66-bit shift register (102), a parity circuit, a latch circuit (103), a 66-bit parallel bus (112, 113) and a dynamic random access memory (DRAM) array (104). Each of these systems interface with control systems (100) of the disk emulator which provide the signals required for the read and write operations of the disk emulator. An error correction process is incorporated in the disk emulator which corrects single bit hard memory errors using only a single parity bit.</p> |
