| 摘要 |
A digital signal processing circuit comprises a digital signal processing section receiving signal data for subjecting the input digital signal data to digital signal processing such as digital filtering or digital equalizing, a data offset imparting circuit receiving output of the digital signal processing section for imparting data offset to the input digital signal data, and a digital-to-analog converter receiving output of the data offset imparting circuit for converting the input digital signal data to analog signal data and delivering out the analog signal data. Data offset is imparted to digital signal data in digital stage after being subjected to a digital signal processing so that a minute fluctuation due to background noise causes little change in MSB in an input to the digital-to-analog converter during inputting of signal data of a small level and linearity adjustment in MSB can be made without causing deterioration in the signal-to-noise ratio in the digital-to-analog converter.
|
