| 摘要 |
<p>PURPOSE:To reduce the effect of dispersion in a gate delay time by ORing with a double clock and inverse of the double clock and using a clock so as to extract the signal being the result of ORing of the said outputs. CONSTITUTION:A clock inverse of 2ck and a data D1 are supplied to two input terminals of an AND gate 41 in an output gate extraction section 40 and a clock 2ck and a data D2 are given to two input terminals of an AND gate 42. Since the clocks 2ck, inverse of 2ck reach an H level alternately, the data D1, D2 are given to an OR gate 52 of an output section 50. Output signals DA, DB of the AND gates 41, 42 are signals being the result of synchronizing the H level of the input signal DI with the clock 2ck. Then the signals DA, DB inputted to the output section 50 are ORed by an OR gate 52, the result is a signal DD synchronously with the clock ck, the signal DD is extracted just in the center by using the clock, inverse of ck by a flip-flop 51 and the result becomes an output data DO. Thus, the effect due to the dispersion in the gates is avoided.</p> |
