发明名称 MULTI-FRAME CONSTITUTION INCLUDING ASYNCHRONOUS SUB-FRAME PATTERN
摘要 PURPOSE:To prevent the pseudo synchronization of a sub-frame from generation by setting the period of the frame pattern of first and second frame pattern preparing circuits so that the period of the frame pattern of a second frame pattern preparing circuit cannot be divided by the period of the frame pattern of a first frame pattern preparing circuit. CONSTITUTION:The number of the repeating bits of a multi-frame pattern cannot be divided by the number of the repeating bits of the sub-frame pattern and as such, the number of respective repeating bits is selected. For example, a sub-frame pattern is made into the repeating pattern of (1, 0, 0, 1) and the repeating pattern of multi-frame patterns (0, 0, 1, 1, 1, 1, 1, 1, 1). As a result, a first sub-frame bit F1 of one multi-frame becomes 1 and the first sub-frame bit F1 of a next multi-frame goes to '0'. Sub-frame bits F2 and F3 are also the same. For this reason, even when first bits A1, B1, C1 and D1 of the low order group data bit of the sub-frame are fixed to '1, 0, 0' and '1' for some reason, the sub-frame pattern is not mistaken.
申请公布号 JPH0235835(A) 申请公布日期 1990.02.06
申请号 JP19880185891 申请日期 1988.07.26
申请人 FUJITSU LTD 发明人 YORITA TAKASHI
分类号 H04J3/06;H04L7/08 主分类号 H04J3/06
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