| 摘要 |
PURPOSE:To eliminate that the output of respective tri-state buffers compete on a bus line by providing a bus control circuit between respective tri-state buffers and a control signal line and constructing to ignore other control signal until a hourly fast control signal is completed. CONSTITUTION:Bus control circuits 61-6n to lie respectively between tri-state buffers 51-5n and control signal lines 41-4n are provided. The bus control circuits 61-6n are formed by inverters 61a-6na and NOR 61b-6nb and reset set flip flops(RS-FF) 61c-6nc. The inverter is connected to a control signal line marked with (-) at an input side and an output side is connected to the resetting side of RS-FF. For the NOR gate, the input side is connected through an inverter to the control signal line marked with (-), connected to a control signal line except the control signal line marked with (-) and an output side is connected to the setting side of the RS-FF. For the RS-FF, the output side is connected to the input side of a tri-state buffer. Thus, the control signal, which becomes earlier a logic 1, is made preferential and other control signal is ignored. |
