发明名称 FRAME SYNCHRONIZING SYSTEM BY SYNCHRONOUS PACKET
摘要 PURPOSE:To easily identify a data packet from a synchronous packet by setting at least one bit in an error detecting code at 0 in the case of setting all bits at 1s and at 1 in the case of setting all bits at 0s when all the header parts of the data packet are set at 1s by using the values 1 or 0 of all bits in the synchronous packet. CONSTITUTION:A data packet forming part 2 forms the data packet by attaching the error detecting code corresponding to a header at an error detection code generating part 3, and synthesizes the output of the error detection code generating part 3 and information data at a synthesizing part 4, and outputs it to a transmission path via the transmission part 6 of the packet. When the header of a formed data packet is the pattern of a part equivalent to the header of the synchronous packet, the error detection code generating part 3 generates the pattern in which no coincidence with the part corresponding to the error detecting code of the synchronous packet is obtained. Since the pattern of the synchronous packet is supplied to a reception part 8 in advance, it is compared with the pattern. In such a way, it is possible to identify whether a reception packet is the synchronous packet or the data packet.
申请公布号 JPH0232637(A) 申请公布日期 1990.02.02
申请号 JP19880181542 申请日期 1988.07.22
申请人 TOSHIBA CORP 发明人 TSUNEYOSHI KAZUYUKI
分类号 H04L7/08 主分类号 H04L7/08
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