| 摘要 |
PURPOSE:To perform smooth and stable current limitation in response to the degree of timewise fluctuation without regard to the range of the load fluctuation by giving an output frequency reduction correcting signal of an inverter with the load fluctuation and by reducing the speed of a motor. CONSTITUTION:A current rate of change arithmetic circuit 4 operates the rate of timewise of the squared value against the output Im of a current effective value detection circuit 3 in every reference cycle designated by a clock oscillator 5. A frequency correction circuit 6 starts its operation on and after the point of time when the current detected value Im against the set value IS of the limited current came up to the relation of Im>IS with a current comparison circuit 7, and it outputs through operation an output frequency reduction corrected value f to an inverter 1. In this way, by letting it a reduction corrected value of the output frequency of the inverter 1, the primary current is reduced down to the limited value and less through a responsive speed reducing drive to an AC motor 2. |
