Test circuit for measuring specific contact resistivity of self-aligned contacts in integrated circuits.

摘要

A test circuit (2000) is described for measuring the specific contact resistivity rc of self- aligned electrodes contacting underlying diffused regions at a major surface of an underlying semiconductor wafer, as well as the sheet (lateral) resistance rs of the underlying diffused regions in some embodiments. The test circuit illustratively includes a pair of test MOS or other type of transistors advantageously made by a self-aligned metallization process simultaneously with the other MOS or other type of transistors to be tested. The two test transistors share a common diffused region (113), a self-aligned common controlled electrode (132) contacting a diffused region underneath it, and a common control electrode (226). During test operation, both test transistors are kept ON by means of an applied above-threshold control voltage (Eg), while a current source (20) forces current through one of the transistors. The resulting voltage (Ve), developed across the common controlled electrode (132) and the controlled electrode (133) of the other transistor is a measure of the specific contact resistivity thereat.