| 摘要 |
PURPOSE: To obtain a submicron class very large scale integrated circuit and multilayered wiring for very high speed integrated circuit technology, by forming a multilayered interconnection wiring, using many mutually related critical processing steps. CONSTITUTION: The forming method comprises the steps of vacuum evaporating Ti of about 100nm and Al 22 contg. Cu about 0.5-10wt.% and Si about 2.5-8wt.% on a paassivation layer 12 and contact vias to form a first level wiring layer, heating an Si substrate to anneal the first level wiring layer, forming a multilayered passivation layer 28 involving a polymer layer 24 having contact vias which expose at least part of the first level wiring layer on this wiring layer, vacuum evaporating a thin Ti layer 32 on the passivation layer 28 and contact vias 26, and vacuum evaporating a thick metal layer 34 having a different compsn. from that of the metal layer 22 on the Ti layer 32 to form a second level wiring layer. |
