| 摘要 |
<p>PURPOSE:To minimize a clock skew by dividing a circuit group to be controlled at their operation by clock signals generated from the same driver and providing each of the divided circuit groups or circuits with a clock driver. CONSTITUTION:Both control signals C1, C2 are turned to 'H' and a clock signal CK is transmitted to circuit groups 13, 14 through clock drivers 15, 16. At that time, a difference of load values observed from clock drivers 15, 16 goes the difference of gate capacity between MOS transistors(TRs) 11 and 12. Thereby the shear of phases of clock signals practically supplied to the circuit groups 13, 14 is proportional to the capacity difference. In this case, the value is fixed independently of the number of circuits in the circuit groups 13, 14. Consequently, a skew between clock signals at the time of increasing the number of parallel processing bits in a digital system can be suppressed to the minimum.</p> |
