发明名称 PHASE SYCHRONIZING CIRCUIT
摘要 PURPOSE:To wade a change in the operating point due to a change in the condition by using a digital counter circuit and a latch circuit so as to attain the digital operation in a synchronizing loop. CONSTITUTION:An input clock pulse is subject to 1/N1 by a frequency divider 1, a latch pulse 7 is outputted and fed to a latch circuit 4. The oscillated frequency from an oscillator 3 is controlled in response to a digital output 6 from the latch circuit 4 in the synchronizing loop and the output of the oscillator 3 is fed to a digital counter circuit 2. An output from the said digital counter circuit 2 is given to the latch circuit 4, which latches a digital input 5 from the digital counter circuit 2 applying 1/N2 frequency division to its output till a new latch pulse 7 is inputted.
申请公布号 JPH0230218(A) 申请公布日期 1990.01.31
申请号 JP19880179219 申请日期 1988.07.20
申请人 NEC CORP 发明人 KODAMA SHIGENORI
分类号 H03L7/091;H03L7/08 主分类号 H03L7/091
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