发明名称 |
Method and apparatus for predicting valid performance of virtual-address to physical-address translations. |
摘要 |
<p>A prediction logic device operating in conjunction with a vector processor to predict, before the completion of the translation of the virtual addresses of all of the data elements of a vector, the valid performace of all virtual-address to physical-address translations for the data elements of the vector. The prediction logic device asserts an MMOK signal to a scalar processor when it becomes known that no memory management fault and/or translation buffer miss will occur such that the scalar processor can resume vector instruction issue to the vector processor at the earliest possible time.</p> |
申请公布号 |
EP0352632(A2) |
申请公布日期 |
1990.01.31 |
申请号 |
EP19890113323 |
申请日期 |
1989.07.20 |
申请人 |
DIGITAL EQUIPMENT CORPORATION |
发明人 |
WILLIAMS, DOUGLAS DAVID;FENWICK, DAVID MARTIN;STANLEY, TIMOTHY JOHN |
分类号 |
G06F12/08;G06F12/10;G06F17/16 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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