SYSTEM FOER BUFFERTMINNE.

摘要

A cache memory comprises a data store STR 40 divided into 4 levels LV0 to LV3, and a corresponding directory store DIR 84 which stores the most significant address (MSA) portions of the addresses of the words stored in the data store. A comparator unit 421 compares the MSA portion of a desired address with the 4 stored MSA portions selected by the least significant address (LSA) portion of the desired address. On a match, the corresponding data word in store 40 is accessed. For no match, the desired word is inserted into the cache under the control of a <> unit 80. A mode control unit 86 generates 2 parity bits for MSA portions as they are written into the directory, and checks them when they are read. …The mode control unit 86 includes two degrade level flip-flops, one for levels 0 and 1 and the other for levels 2 and 3. A parity error on a successful match sets the corresponding flip-flop, thereby disabling the pair of levels in which the error occurred, so that the cache then operates with only 2 levels. An error in the remaining 2 levels sets the other flip-flop and disables the cache completely.