| 摘要 |
<p>The invention relates to an analog-digital converter having a structure with several identical cascaded stages each converting a group of p bits in decreasing significance order. Each stage comprises a partial analog-digital converter (PADC) receiving an input signal Si and delivering p bits, a partial digital-analog converter (PDAC) re-converting these p bits into an analog signal, a subtractor (D) taking the difference between the input signal and the p re-converted bits, and an amplifier (AP) with gain 2<p> to rescale the difference signal with a view to conversion of this difference in a following stage identical to the first. According to the invention, in order to take account of the error on the gain 2<p> due to the fact that the amplifier AP is constructed from an operational amplifier with finite gain G and not infinite gain, there is provision for the reference voltage Vi used for the conversion in a stage to be equal to the reference voltage of the preceding stage, modified by a correction coefficient exactly equal to the error introduced. A calibration amplifier using an operational amplifier with the same finite gain G enables automatic establishing of the reference voltage of a stage from that of the preceding stage. <IMAGE></p> |
