| 摘要 |
<p>PURPOSE:To surely prevent the destruction of data in a memory by respectively providing a dummy word line composed of the same material as that of a word line and a dummy transistor having the same size as that of a selective transistor and setting timing for precharge. CONSTITUTION:The delay quantity of a delay circuit 7 to delay the change of a clock signal CL corresponding to the end of the writing/reading of memory data is made equal to that of a word line WL or larger. Thus, after the ends of all the word lines WLs become a non-selective state in synchronism with the change of the signal CL, plural bit lines BLs are precharged to a prescribed potential by plural precharge FETs 11, 11', 12, and 12' controlled by the output of the delay circuit 7 and further, the next column address data are latched by a latch circuit 13 controlled by the output of the delay circuit 7. Consequently, the change of the output of a column address decoder 16 can be prevented until the end of the word line becomes the non-selective state.</p> |
