发明名称 Circuit implementation of block matching algorithm
摘要 A circuit for implementing a full search block matching algorithm for coding video signals sequentially receives pixel values from a block of pixels in a current video frame and sequentially receives pixel values from a search area of a previous video frame. The circuit includes a plurality of processors for calculating in parallel a group of error functions corresponding to a group of positions of the block in the search area. The error functions are compared for determining the block position having the minimum error function.
申请公布号 US4897720(A) 申请公布日期 1990.01.30
申请号 US19880167327 申请日期 1988.03.14
申请人 BELL COMMUNICATIONS RESEARCH, INC. 发明人 WU, LANCELOT;YANG, KUN-MIN
分类号 H04N7/32;G06T7/00;G06T7/20;H04N5/14;H04N7/26 主分类号 H04N7/32
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