| 摘要 |
<p>PURPOSE:To increase the margin at phase matching by dividing the frequency of an input clock and an output clock at a prescribed frequency division ratio so as to apply phase decision. CONSTITUTION:A serial/parallel conversion section 3 uses an input clock CK 1 subjected to, e.g., 1/2 frequency division at the 1st frequency divider section 2 so as to convert an output data of an input buffer 1 into a parallel data corresponding to the frequency division ratio. A clock outputted from a phase control section 8 is a noninverting or inverting clock being subjected to 1/2 frequency division of an output clock CK 2 at the 2nd frequency divider section 6 according to the result of decision by a phase deciding section 7. A selection section 4 selects either of two parallel output data from the serial parallel conversion section 3 depending on the logic value of the clock and gives the result to an output buffer 5. Thus, the relation of phase between the input data to the output buffer 5 and the output clock CK 2 is unchanged and the phase margin is ensured over a range close to 180 deg. except the cross points the same as the case with a fixed phase.</p> |
