| 摘要 |
The circuit for obtaining the time delay of output signal (Vo) at rising edge or falling edge selectively by applying certain input signal (Vi) to a PMOS transistor (1) and NMOS transistor (2) simutaneously includes a PMOS transistor (1) receiving input power through source, a source grounded NMOS transistor (2), and a depletion transistor (3) having time delay in the rising edge and falling edge, and a second delay circuit for constant time delay regardless of the input voltage variation.
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