CLOCK ASYNCHRONOUS DATA DETECTOR

摘要

PURPOSE:To eliminate the need for any preamble bit by discriminating a reception signal by an oscillator output with a specific frequency, separating a data at an interval of n-bit from the discriminated pulse signal and extracting in total n-set of data series. CONSTITUTION:An output of a demodulator 10 is given to a sign discriminator 12, which discriminates the sign of the data signal by using the output of a clock oscillator 14 oscillated at a frequency nearly equal to the frequency being n-times the clock frequency of the received data signal as the clock pulse. Pulses are produced from pulse distribution circuits 18-1-18-n at an interval of n-bit from the output pulse train of the clock oscillator 14 respectively and the signal subject to sign discrimination by the sign discriminator 12 is subject to n-branching and its output is given to a memory 24-i and an error detection circuit 22-i. Since it is not required to generate a clock pulse synchronously with the reception signal, the preamble bit required for clock synchronization is eliminated.