| 摘要 |
<p>PURPOSE:To effectively decrease jitter quantity regardless of the size of a repeating distance by generating a clock signal depending on the code pattern of an input code to have a normal phase error so that a jitter between these code patterns can be corrected. CONSTITUTION:In a PLL circuit to be composed of a phase comparator, a charge pump circuit 4-2, a loop filter 4-3 and a voltage control oscillator 4-4, a leak current source is added to one of current sources in the charge pump circuit 4-2. Then, when input signal patterns are wholly '0' and wholly '1', the period of an input signal in the PLL circuit 4 goes to be different. Accordingly, the influence of the leak current is different by the pattern and pattern dependency is generated in the normal phase error. When the quantity of the jitter is negative, the leak current source is set so that the value of the normal phase error in case of the full '1' pattern can be larger than the value of the error in case of the full '0' pattern. Thus, a jitter characteristic can be shifted to a positive side and improved without changing an optimum equalizing point.</p> |
