| 摘要 |
PURPOSE:To increase arithmetic processing speed for extraction of the square root by supplying the output of a bit inverting circuit to a rounding circuit via a multiplexer only in a partial arithmetic process for extraction of the square root and performing a right shift by one bit after addition of 1 to the minimum digit. CONSTITUTION:A multiplexer 8 supplies the output of a bit inverting circuit 7 to a rounding circuit 6 only in a partial arithmetic process for extraction of the square root. The output of the circuit 7 receives 1 at its minimum digit and is shifted to the right by one bit in the circuit 6. Otherwise the output of a right shift circuit 5 is supplied directly to the circuit 6 via the multiplexer 8. Thus it is possible to perform the binary calculation of 1/2*(3-AXi) where 0<AXi<=1 is satisfied in a single step via an arithmetic processor capable of the multiplication of floating points just with addition of the circuit 7 and the multiplexer 8. Then the repetitive calculation is carried out at high speed for the extraction of the square root. |
