| 摘要 |
PURPOSE:To reduce the amount of hardware by decoding all code extension parts of multiples outputted from multiple generators to obtain the sum of code extension and simplifying the addition form to reduce the number of input lines to an adding circuit. CONSTITUTION:At the time of multiplication between contents of a multiplicand holding register 3 and contents of a partial multiplier holding register 4 in each of partial multiplication blocks 2-1 to 2-4, a numerical value N of the decoded result for each group of 2-bit sections of contents of the register 4 is generated by a decoder 5 conforming to a 2-bit booth algorithm, and the product between the numerical value N and the multiplicand is operated in a multiplier 6 for each group to generate the partial product for each group. Partial products are added by a multi-stage carry maintaining adder 8, and the final result is obtained by a carry look ahead adder. Output results of a decoder 7 of code extension parts are added to the adder 8. All code extension parts are decoded to obtain the sum of code extension by the decoder 7. |
