| 摘要 |
A video processing circuit which is capable of freely expanding and contracting the image in the vertical direction. To the phase comparator input of the PLL circuit (12) are input a vertical synchronizing signal of a video signal and a signal from VCO in the PLL circuit of which the frequency is divided by the number N of sampling lines in the vertical direction. The signals of a frequency N times as great as the frequency of the vertical synchronizing signals are taken out, and are utilized as address signals in the vertical direction for the image memory (20). |
