| 摘要 |
PURPOSE:To access a non-volatile memory without the latency time by providing a transfer control part with an inter-memory bus independently to transfer data between a dual port memory part and a non-volatile memory part independently of the operation of a CPU. CONSTITUTION:It is supposed that processing contents of a CPU 5 are switched from a processing A to a processing B. A start signal and a direction are given to a transfer control part 3 from a register 4 by the indication of the CPU 5, and a control signal is sent to a non-volatile memory part 2. Stored contents of a RAM 6 which are temporarily stored in a dual port memory part 1 are transferred to the memory part 2. Though this transfer processing time is long because of a low speed, the CPU 5 can start the data processing B and following processings without waiting because the data bus for the CPU 5 is not used during said data transfer. |
