| 摘要 |
PURPOSE:To increase the degree of integration by not containing MOS transistors in a memory cell, and increase the reading speed by reducing the resistance value of a conductive layer, by boring contact holes in a dielectric layer, according to information to be stored at crossing points of a belt-type conductive layer and a belt-type metal wiring, and forming PN junctions in a single crystal silicon layer of the crossing points in which at least the contact hole is bored. CONSTITUTION:A single crystal silicon layer 7 exists at crossing parts of conducive layers 11, 12, 13 and metal wirings 41, 42, 43. In order to mutually isolate the single crystal layer 7, trenches are arranged, in which a silicon oxide film 3 is buried. In a silicon oxide film 4, contact holes are arranged according to information to be written. In the part of the silicon oxide film 4 where the contact holes are arranged, P-type impurity is introduced in the single crystal silicon layer 7, and a P-type conductive layer 6 is formed. |
