| 摘要 |
<p>A phase adjusting circuit for adjusting a phase of each bit of serial data (D1) by synchronizing with a system clock (CK2), comprising a plurality of registers (31, 32, 33, 34); inputting each bit of the data into a corresponding one of the plurality of registers (31, 32, 33, 34) in a predetermined cyclic order, synchronized with a receiving clock (CK1) which is extracted from the data, and outputting outputs of the registers (31, 32, 33, 34) in parallel. The outputs are each selected in a selector circuit (44) under a control of the selector control signal in the same order as the above input into the registers (31, 32, 33, 34). The selector control signal is generated by detecting a phase relationship between phases of the receiving clock (CK1) and the system clock (CK2), and generating a selector control signal having phase which is determined according to the phase relationship. Then, each bit of the above selected output is synchronized with the system clock (CK2).</p> |
