发明名称 EXTERNAL SYNCHRONIZING CLOCK PULSE GENERATING CIRCUIT
摘要 PURPOSE:To operate an identification retiming circuit for a receiver even at the point of time of an external clock pulse input or in the presence of momentary interruption, and to prevent out of synchronism by providing a clamp circuit between a low pass filter and a voltage controlled oscillator and clamping the control voltage input of the voltage controlled oscillator to a prescribed operating range. CONSTITUTION:The circuit is constituted in such a way of a control voltage input of the voltage controlled oscillator 6 is clamped to a prescribed operating range by a clamp circuit 4 provided between the low pass filter 3 and the voltage controlled oscillator 6, clamping the output of the low pass filter 3 to a prescribed voltage range to obtain a control voltage 5. Moreover, the voltage controlled oscillator 6 generates a clock pulse output 7 having a frequency in response to the control voltage 5. Thus, even if the initial phase difference between the external clock pulse input 1 and the clock pulse output 7 is in any state at the point of time of external clock pulse input or in the presence of momentary interruption, the identification retiming circuit of the receiver is operated normally thereby preventing out of synchronism.
申请公布号 JPH0221725(A) 申请公布日期 1990.01.24
申请号 JP19880170973 申请日期 1988.07.11
申请人 NEC CORP 发明人 NISHIKAWA KAZUO
分类号 H03L7/093;H03L7/08;H03L7/14;H04L7/04 主分类号 H03L7/093
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