| 摘要 |
PURPOSE:To obtain the logic array of high speed brought to dynamic driving by one clock pulse train by pre-charging each input line to the power source potential in a pre-charge period and interrupting each transistor and supplying an input signal to the input line in a sampling period. CONSTITUTION:A first gate circuit 1 and a second gate circuit 2 constitute an AND array and an OR array, respectively, a NAND gate circuit 3 constitutes an input control circuit, and a NAND gate 23 sets forcibly its output to '1' when a clock pulse phi'A is in a low level. In a period t0, phi'A is in a low level, pre-charge FETs P0P-P3P become ON, and discharge FETs N0S-N3S become OFF. As for the second gate circuit 2, discharge FETs N0P-N3P become ON, and also, P0-P7 for constituting OR all become OFF since the output line of the first gate circuit is pre-charged. In such a way, the circuit constitution is facilitated due to dynamic driving of only one clock pulse. |
