| 摘要 |
PURPOSE:To eliminate the synchronizing error between a microprocessor kept in a break state and a target system by always designate the ready signal inputted to the microprocessor via the target system. CONSTITUTION:A controller 2 outputs a high level while a microprocessor 1 is kept in a break state and the address set by a switch 10 is outputted to a target system via a fixed address buffer 7. The target system outputs a ready signal READY18 and the target data 12 based on a read signal 22. Then the signal READY18 is inputted to the controller 2 and the microprocessor 1. Thus the microprocessor 1 uses the signal READY18 of the target system to give an access to a break memory 3. As a result, the synchronizing error is avoided between the microprocessor 1 and the target system. |
