发明名称 Data processor having integrated circuit memory refresh
摘要 An improved data processor architecture is provided having integrated circuit (IC) memories. Provision is made for dynamic memories with a memory refresh arrangement. Memory refresh is provided in response to instruction execution, synchronized with computer control signals to minimize contention or conflicts with computer operations and to share control circuitry.
申请公布号 US4896260(A) 申请公布日期 1990.01.23
申请号 US19890343112 申请日期 1989.04.24
申请人 HYATT, GILBERT P. 发明人 HYATT, GILBERT P.
分类号 B60R16/02;B60R16/037;F21V23/00;G01S7/52;G01S15/89;G02F1/133;G03F9/00;G04G99/00;G05B19/35;G05B19/408;G05B19/409;G05B19/4093;G05B19/414;G06F12/00;G06F13/12;G06F13/16;G06J1/00;G07G1/12;G10L19/00;G11C11/406;G11C11/56;G11C19/28;G11C19/36;G11C27/00;G11C27/02;G11C27/04;(IPC1-7):G06F12/00 主分类号 B60R16/02
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