PROGRAMMABLE WORD LENGTH AND SELF - TESTING MEMORY IN A GATE ARRAY WITH BIDIRECTIONAL SYMMETRY

摘要

Core cells are disposed in at least two rows and have an internal configuration of two semiconductor devices. Adjacent core cells within each row is repetively duplicated within the row ith respect to the internal configuration of the semiconductor devices within each core cell disposed in the semiconductor chip. The semiconductor device comprising one core cell has a mirror symmetrical relationship with a corresponding semiconductor device comprising a second core cell within the row.